The present invention relates to home networks, and more particularly to a method and system for performing a two-step read as an atomic read in a home network.
HomePNA or HPNA is a de facto home networking standard developed by the Home Phoneline Networking Alliance. HPNA allows all the components of a home network to interact over the home""s existing telephone wiring without disrupting voice capability. In the same way a LAN operates, home networking processes, manages, transports and stores information, which enables disparate devices in a home network such as telephones, fax machines, desktops, laptops, printers, scanners and Web cameras to connect and integrate over an existing wiring topology.
To create the home network, personal computers may be equipped with a HPNA network and HPNA software. An HPNA network may be implemented as an internal PC network interface card (NICs) that includes telephone jacks on the back for connection to the network. An HPNA network may also be implemented as a chipset or as an external USB adapter that plugs into the USB port on the PC on one end, while the other end connects to the phone line at the wall jack.
FIG. 1 illustrates an embodiment of a home phone line network that complies with the Home Phoneline Networking Alliance (HPNA) specification version 2.0. The network allows multiple computers to communicate through telephone wires of residential homes. The network includes an application program running on the PC called a host media access controler (MAC) 112, and a control chip 100 for implementing the HPNA 2.0 specification, which is included on a network interface card. The control chip 100 includes a Media Independent Interface (MII) 106, a Media Access Controller (MAC) 108, and a Physical Layer (PHY) 110. The MAC 108 includes several 32-bit registers for maintaining statistics regarding frame transmission and reception on the home network. These registers are accessible by the host MAC 112 so that a user may monitor and diagnose the system. The MII 106 receives the request from the host MAC 112 to read the MAC registers by issuing a read request signal. The MII 106 also includes its own internal registers that are 16 bits in length, which dictates that the MII 106 is only capable of reading 16 bits at a time.
Therefore, when the MII 106 needs to read one of the 32-bit MAC registers, a two-step read operation is necessary in which the MII 106 reads the lower half of the register first followed by the upper half of the register. The problem is that the MAC registers are updated by an increment signal that increments the value in the registers. Periodically, the increment signal and the read signal from the MII 106 occur simultaneously. The result is that when the MII 106 performs its two-step read and reads the lower half of the register in the first step, the lower half of the register may get incremented and overflow into the upper half of the register before the upper half is read. This will result in an incorrect value being read from the register.
Accordingly, what is needed is a method and system for performing a two-step read on the MAC registers as if one atomic read had been performed so that the correct value is always read from the registers. The present invention addresses such a need.
The present invention provides a method and system for performing a two-step read on a count register as an atomic read in a home network. The count register has a lower half and an upper half, and is incremented in response to an increment signal and is read in response to a read signal. The method and system include reading the lower half of the count register and storing the upper half of the count register in a shadow register in response to detecting the increment signal. The shadow register is then read in order to obtain the value of the upper half of the count register.
According to the system and method disclosed herein, the present invention assures that reading an incorrect value from the upper half of the count register due to any overflow condition is avoided.